Synopsis

San Jose-headquartered Cadence Design Systems provides electronic design automation (EDA) software, hardware and intellectual property (IP) used to design semiconductors, integrated circuits and systems-on-chips (SoCs).

ETtech

India can develop a domestic semiconductor startup ecosystem comparable in scale and vibrancy to that of the US within the next decade, said Paul Cunningham, senior vice-president and general manager of the System Verification Group at Cadence.



“I firmly believe that within 10 years from now, we’ll have every bit as vibrant and significant a local semiconductor startup industry as we have in the US,” Cunningham told ET. “It’s absolutely coming, and we want to be a part of that.”



San Jose-headquartered Cadence Design Systems provides electronic design automation (EDA) software, hardware and intellectual property (IP) used to design semiconductors, integrated circuits and systems-on-chips (SoCs).

The company on July 27 said while announcing its results for the June quarter that artificial intelligence (AI) demand helped core EDA revenue increase 18% year-on-year, while hardware added 12 new customers. It also raised its 2026 revenue outlook to $6.26-$6.34 billion and reported a record $8.1 billion backlog.



India is already central to Cadence’s operations, product development and customer base. Cunningham estimated that the country accounts for roughly a third of the company’s global workforce, spread across multiple locations. Many of Cadence’s largest customers also have substantial engineering operations in India, so local teams help shape the company’s products and roadmaps.



“The talent pool is phenomenal,” he said. “A lot of the execution is out here. Our products and roadmaps are shaped by our users, their needs and their challenges, and a lot of that is also coming from India.”



Cadence plans to continue expanding its India workforce, although Cunningham said hiring and periodic restructuring could happen simultaneously as the company reallocates investments. “You take a net view, we’ve grown a lot and we’re going to continue to grow in India,” he said. “There’s no change in that mindset.”



AI now features in about 80% of Cunningham’s discussions with customers. Chipmakers are incorporating AI into their own products while also looking to AI-enabled design tools to address growing complexity and shorten development cycles.



Cadence has dedicated hundreds of staff members across its product line-up to build AI agents that automate chip design and verification tasks. Its broader AgentStack strategy includes ChipStack for digital front-end design and verification, InnerStack for physical implementation and sign-off, Verisium for verification and AuraStack for advanced packaging and boards.



ChipStack, the first of these offerings to be announced, has reached its second major release. Cadence is working on about 25 “serious engagements” with leading customers, Cunningham said, with deployments ranging from tens to hundreds of users. Some customers are using the technology on production programmes rather than limiting it to pilots.



However, Cunningham cautioned that adoption had not yet reached broad scale, which Cadence defines as deployments involving thousands of users.



“It is still early,” he said. “This overall agentic transformation in chip design is going to take another couple of years to proliferate fully.”



Cadence has recorded cases in which AI agents reduced five-week tasks to one week, five-day assignments to a day and day-long jobs to a few hours. The gains span design creation, verification planning, test-bench generation and formal verification checkers.



“The big challenge is being able to do it everywhere, all the time, predictably and reliably,” Cunningham said. “There’s still a lot of work to do there.”



Human in the loop



Despite increasing automation, Cadence is keeping engineers in the loop. In some of the most advanced cases, agents can operate autonomously for 12 to 24 hours before checking back with a user. Many practical applications, however, involve handing an agent a task that takes between five and 20 minutes.



Final approval for critical stages such as chip sign-off will continue to rest with engineers or Cadence’s established, non-agentic tools.



“If you’re going to do a sign-off, the ultimate yes or no is still going to go with our non-agentic products,” Cunningham said. “The agents may be running our non-agentic products, but we would still use our proven, certified software to do the sign-off.”



The effectiveness of agents also depends heavily on how clearly engineers define a task. Cunningham likened natural-language instructions to another form of programming, arguing that the workforce will have to develop the ability to manage and instruct AI systems.



“An agent is not psychic,” he said. “You can ask what you want in natural language, but you still have to speak clearly.”



Over the next five years, Cunningham expects individual engineers to supervise teams of 10, 20 or even 100 agents. The key skill will be ensuring that those agents act productively rather than simply handing over entire workflows without oversight.



Early adoption



India is participating in Cadence’s early AI-agent deployments through the local operations of global semiconductor companies. Cunningham described Indian engineering teams as progressive and willing to experiment with the technology.



“There’s a lot of appetite and a lot of energy,” he said. “It’s still early adoption, so you have to have that enthusiasm.”



Cadence is also going to participate in the next phase of India’s semiconductor policy. Jayashankar Narayanankutty, group director for sales in India at Cadence, said, "We're still awaiting the detailed operating contours of India Semiconductor Mission 2.0, but see significant opportunities in its focus on design, strategic electronics, research and domestic capability development."



Narayanankutty said the number of companies in the government’s semiconductor design-linked incentive programme had grown from around 30, when it was notified, to 105. "We believe the next phase could expand the domestic ecosystem substantially, potentially taking the number of companies to around 500 over five years," he said.



He highlighted an area of particular interest: request for proposal-based development of strategic electronics.



Provisions allowing overseas citizens of India to participate in the programme could encourage experienced semiconductor executives of Indian origin to return and establish companies in the country, he said.



While access to risk capital has improved over the past three years, finding skilled engineers at costs that startups can afford remains a challenge, Narayanankutty said.



Cadence is working with educational institutions, including IIT Delhi, to help prepare engineers with skills that can be deployed in the semiconductor industry. The company is also engaging individually with chip startups, offering arrangements based on their specific requirements rather than relying on a standardised programme.



Cunningham said India’s startup base was still small enough for Cadence to provide such customised support.



“There just isn’t that startup volume yet,” he said. “If there were thousands of startups, we would need a different kind of model. Right now, it’s a small community, and we work with each one.”



Cadence also sees scope for deeper collaboration between industry and academia. Providing universities with access to EDA tools is only the beginning, Narayanankutty said, adding that the next stage must include research and joint contributions capable of building IP (intellectual property) and commercial semiconductor products.



For Cadence, the growth opportunity is being fuelled by both the global expansion of the semiconductor industry and the increasing size and complexity of chips, Cunningham said. “More chips, bigger chips, it all helps,” he said.

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